LOW VOLTAGE, LOW POWER CMOS OPERATIONAL AMPLIFIER INPUT STAGE

Abstract

The lowering of the power supply and voltage has an enormous impact on the signal to noise ratio (SNR) of analog circuits. The SNR decreases because of the lower allowable signal voltages and also because of higher noise voltages due to low supply currents. To maximise SNR, we have to make the signal as large as possible ideally from rail to rail. Nowedays trend howards low voltage and low power design are mainly driven by the technological limitations of high performances VLSI systems and the increasing demands for long life equipment. It is well known that rail-to-rail mode operational amplifier with a high common mode rejection ratio are in growing interest. In this work, we are interested on a particular structure of a CMOS input operational amplifiers stages, used very frequentely in analog circuits, for instrumentation applications in very large scale integration (VLSI). Our study relates to a particular differential input stage which functions in rail-to-rail mode( from the positive bias voltage VDD to the negative one VSS ) The principal performances aimed for the input stage are a common mode gain as low as possible, a differential gain and a band-width rather high and as possible the most constant on all the common mode range. Finally, we can affirm that the predictions under our consideration at the beginning were confirmed by electric simulation.