Vers une approche combinant SysML et Model Checking pour la vérification formelle des propriétés dynamiques

Abstract

Since SysML is a rapidly emerging system modeling language as a de facto standard used for software specifications, SysML sequence diagrams provide a visual technique for modeling and describing software behaviors. However, sequence diagrams can not be used to automatically analyze and verify software behavior due to the lack of formal semantics. To ensure the reliability of the systems software, a description of the behavior and a formal verification approach are proposed in this project, using SysML sequence diagram and timed automata model. First, a complete relationship is established between the sequence diagram and the timed automata network from defined transformation rules. Then, the model transformation will be established using the predifined rules. Finally formal verification can then be performed to verify TCTL-based domain properties as unambiguous expressive logic with an Automated Model Checker (UPPAAL). Our proposal bridges the gap between semi-formal and formal software modeling, and advance the verification step as early as possible in the heterogeneous systems development cycle. Our approach has been evaluated on an ATM simulation system. The case study shows that this proposed approach is effective and in the behavior, description and formal verification of the software.